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| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001,2002 mos integrated circuit pd16732d 384-output tft-lcd source driver (compatible with 64-gray scales) data sheet document no. s15022ej1v0ds00 (1st edition) date published june 2002 ns cp (k) printed in japan description the pd16732d is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 + 0.1 v to v dd2 ? 0.1 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a maximum clock frequency of 65 mhz when driving at 3.0 v, 45 mhz when driving at 2.3 v, this driver is applicable to xga-standard tft-lcd panels and sxga tft-lcd panels. features ? cmos level input (2.3 to 3.6 v) ? 384 outputs ? input of 6 bits (gray-scale data) by 6 dots ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter ? logic power supply voltage (v dd1 ): 2.3 to 3.6 v ? driver power supply voltage (v dd2 ): 8.0 to 9.0 v ? high-speed data transfer: f clk = 65 mhz (internal data transfer speed when operating at v dd1 = 3.0 v) ? output dynamic range: v ss2 + 0.1 v to v dd2 ? 0.1 v ? apply for dot-line inversion, n-line inversion and column line inversion ? output voltage polarity inversion function (pol) ? display data inversion function (capable of controlling by each input port) (pol21,pol22) ? current consumption control function (lpc, bcont) ? succession of pd16732a driver ordering information part number package pd16732dn-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, so please contact one of our sales representatives. the mark shows major revised points.
data sheet s15022ej1v0ds 2 pd16732d 1. block diagram sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 - v 9 pol d 00 - d 05 c 1 c 2 c 63 c 64 stb clk 64-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 - d 15 d 20 - d 25 s 3 s 384 pol21,pol22 d 30 - d 35 d 40 - d 45 d 50 - d 55 bcont lpc remark /xxx indicates active low si gnal. 2. relationship between output circuit and d/a converter s 1 s 2 s 383 6-bit d/a converter s 384 v 4 5 5 pol multi- plexer v 9 v 0 v 5 data sheet s15022ej1v0ds 3 pd16732d 3. pin configuration (top of copper foil surface, face-up) pd16732dn-xxx: tcp (tab package) s 384 s 383 sthl s 382 d 55 s 381 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 v dd1 r , /l v 9 v 8 v 7 v 6 v 5 v dd2 v ss2 bcont v 4 v 3 v 2 v 1 v 0 v ss1 lpc clk stb pol pol21 pol22 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 s 4 d 03 s 3 d 02 s 2 d 01 s 1 d 00 sthr c o pp er f oil surface remark this figure does not specify the tcp package. data sheet s15022ej1v0ds 4 pd16732d 4. pin functions (1/2) pin symbol pin name i/o description s 1 to s 384 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input the shift direction control pin of the shift register. the shift directions of the shift registers are as follows. r,/l = h (right shift): sthr (input), s 1 s 384 , sthl (output) r,/l = l (left shift) : sthl (input), s 384 s 1 , sthr (output) sthr right shift start pulse i/o sthl left shift start pulse i/o these refer to the start pulse i/o pins when the ic is connected in cascade. loading of display data starts when a high level is read at the rising edge of clk. a high level should be input as the pulse of one cycle of the clock signal. if the start pulse input is more than 2clks, the first 1clk of the high-level input is valid. r,/l = h (right shift): sthr input, sthl output r,/l = l (left shift): sthl input, sthr output clk shift clock input this pin refers to the shift clock input of the shift register. the display data is loaded into the data register at the rising edge. at the rising edge of the 64th after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. when the 66 clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stb?s rising edge. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. in addition, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input input pol = l: the s 2n?1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2n?1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n-1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stb?s rising edge. pol21, pol22 data inversion input select of inversion or no inversion for input data. pol21: d 00 -d 05 , d 10 -d 15 , d 20 -d 25 data inversion or no inversion of port1 pol22: d 30 -d 35 , d 40 -d 45 , d 50 -d 55 data inversion or no inversion of port2 pol21,pol22 = h: data are inverted in the ic. pol21,pol22 = l: data are not inverted in the ic. lpc low power control input the current consumption is lowered by controlling the constant current source of the output amplifier. in low power mode (lpc = l), the v dd2 of static current consumption can be reduced to two thirds of the normal current consumption. this pin is pulled up to the v dd1 power supply inside the ic. lpc = h or open: normal power mode lpc = l: low power mode bcont bias control input this pin can be used to finely control the bias current inside the output amplifier. in cases when fine-control is necessary, connect this pin to the stabilized ground potential (v ss2 ) via an external resistor of 10 to 100 k ? (per ic). when this fine-control function is not required, leave this pin open. refer to 9. current consumption reduction function data sheet s15022ej1v0ds 5 pd16732d (2/2) pin symbol pin name i/o description v 0 to v 9 -corrected power supplies ? input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v v dd1 logic power supply ? 2.3 to 3.6 v v dd2 driver power supply ? 8.0 to 9.0 v v ss1 logic ground ? grounding v ss2 driver ground ? grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down (simultaneous power application to v dd2 and v 0 to v 9 is possible.). 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also recommended between the -corrected power supply terminals (v 0 , v 1 , v 2 ,....., v 9 ) and v ss2 . data sheet s15022ej1v0ds 6 pd16732d 5. relationship between input data and output voltage value the pd16732d incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd?s counter electrode voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors (r 0 to r 62 ) are designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ? to v 63 ? is almost equivalent as shown in figure 5-2. for the 2 sets of five -compensated power supplies, v 0 to v 4 and v 5 to v 9 , respectively, input gray scale voltages of the same polarity with respect to the common voltage. when fine-gray scale voltage precision is not necessary, there is no need to connect voltage follower circuit to the ?corrected power supplies v 1 to v 3 and v 6 to v 8 . figure 5?1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , and -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships as follows. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v figures 5?2 indicates -corrected voltages and ladder resistors ratio. figures 5?3 indicates the relationship between the input data and output voltage and the resistance values of the resistor string. figure 5?1. relationship between input data and -corrected power supplies 0.1 v 0.1 v v dd2 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 0.5 v dd2 v 9 v ss2 00 10 20 30 3f input data (hex) 15 15 16 16 16 16 16 16 split interval data sheet s15022ej1v0ds 7 pd16732d figure 5?2. -corrected voltages and ladder resistor?s ratio v 0 ' v 17 ' v 1 ' v 47 ' v 2 ' v 48 ' v 3 ' v 49 ' v 15 ' v 16 ' v 63 ' v 61 ' v 62 ' r 0 r 17 r 1 r 47 r 46 r 2 r 48 r 3 r 49 r 14 r 15 r 16 r 60 r 61 r 62 v 4 v 3 v 1 v 0 v 17 '' v 0 '' v 16 '' v 15 '' v 2 '' v 1 '' v 63 '' v 62 '' v 61 '' v 49 '' v 48 '' v 47 '' r 61 r 60 r 59 r 49 r 48 r 47 r 46 v 6 r 62 v 5 r 17 r 0 r 16 r 15 r 14 r 2 r 1 v 9 v 8 v 60 '' rn ratio1 ratio2 value( ? ) r0 8.0 0.050 800 r1 7.5 0.047 750 r2 7.0 0.044 700 r3 6.5 0.041 650 r4 6.0 0.038 600 r5 5.5 0.035 550 r6 5.5 0.035 550 r7 5.0 0.032 500 r8 5.0 0.032 500 r9 4.0 0.025 400 r10 4.0 0.025 400 r11 3.5 0.022 350 r12 3.5 0.022 350 r13 3.5 0.022 350 r14 3.0 0.019 300 r15 3.0 0.019 300 r16 3.0 0.019 300 r17 2.5 0.016 250 r18 2.5 0.016 250 r19 2.5 0.016 250 r20 2.0 0.013 200 r21 2.0 0.013 200 r22 2.0 0.013 200 r23 1.5 0.009 150 r24 1.5 0.009 150 r25 1.5 0.009 150 r26 1.5 0.009 150 r27 1.0 0.006 100 r28 1.0 0.006 100 r29 1.0 0.006 100 r30 1.0 0.006 100 r31 1.0 0.006 100 r32 1.0 0.006 100 r33 1.0 0.006 100 r34 1.0 0.006 100 r35 1.0 0.006 100 r36 1.0 0.006 100 r37 1.0 0.006 100 r38 1.0 0.006 100 r39 1.0 0.006 100 r40 1.0 0.006 100 r41 1.0 0.006 100 r42 1.0 0.006 100 r43 1.0 0.006 100 r44 1.0 0.006 100 r45 1.0 0.006 100 r46 1.0 0.006 100 r47 1.0 0.006 100 r48 1.0 0.006 100 r49 1.0 0.006 100 r50 1.0 0.006 100 r51 1.0 0.006 100 r52 1.0 0.006 100 r53 1.5 0.009 150 r54 1.5 0.009 150 r55 1.5 0.009 150 r56 2.0 0.013 200 r57 2.0 0.013 200 r58 2.5 0.016 250 r59 2.5 0.016 250 r60 3.0 0.019 300 r61 5.0 0.032 500 r 62 8 . 0 0 . 0 5 0 800 caution there is no connection between v 4 and v 5 terminal in the chip. remark the resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. the resistance ratio2 is a relative ratio in the case of setting the total resistance to 1. data sheet s15022ej1v0ds 8 pd16732d figure 5?3. relationship between input data and output voltage (pol21,pol22 = l) (output voltage 1) v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 (output voltage 2) 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v input data 00h v 0' v 0 v 0'' v 9 01h v 1' v 1 +(v 0 -v 1 ) 7250 / 8050 v 1'' v 9 +(v 8 -v 9 ) 800 / 8050 02h v 2' v 1 +(v 0 -v 1 ) 6500 / 8050 v 2'' v 9 +(v 8 -v 9 ) 1550 / 8050 03h v 3' v 1 +(v 0 -v 1 ) 5800 / 8050 v 3'' v 9 +(v 8 -v 9 ) 2250 / 8050 04h v 4' v 1 +(v 0 -v 1 ) 5150 / 8050 v 4'' v 9 +(v 8 -v 9 ) 2900 / 8050 05h v 5' v 1 +(v 0 -v 1 ) 4550 / 8050 v 5'' v 9 +(v 8 -v 9 ) 3500 / 8050 06h v 6' v 1 +(v 0 -v 1 ) 4000 / 8050 v 6'' v 9 +(v 8 -v 9 ) 4050 / 8050 07h v 7' v 1 +(v 0 -v 1 ) 3450 / 8050 v 7'' v 9 +(v 8 -v 9 ) 4600 / 8050 08h v 8' v 1 +(v 0 -v 1 ) 2950 / 8050 v 8'' v 9 +(v 8 -v 9 ) 5100 / 8050 09h v 9' v 1 +(v 0 -v 1 ) 2450 / 8050 v 9'' v 9 +(v 8 -v 9 ) 5600 / 8050 0ah v 10' v 1 +(v 0 -v 1 ) 2050 / 8050 v 10'' v 9 +(v 8 -v 9 ) 6000 / 8050 0bh v 11' v 1 +(v 0 -v 1 ) 1650 / 8050 v 11'' v 9 +(v 8 -v 9 ) 6400 / 8050 0ch v 12' v 1 +(v 0 -v 1 ) 1300 / 8050 v 12'' v 9 +(v 8 -v 9 ) 6750 / 8050 0dh v 13' v 1 +(v 0 -v 1 ) 950 / 8050 v 13'' v 9 +(v 8 -v 9 ) 7100 / 8050 0eh v 14' v 1 +(v 0 -v 1 ) 600 / 8050 v 14'' v 9 +(v 8 -v 9 ) 7450 / 8050 0fh v 15' v 1 +(v 0 -v 1 ) 300 / 8050 v 15'' v 9 +(v 8 -v 9 ) 7750 / 8050 10h v 16' v 1 v 16'' v 8 11h v 17' v 2 +(v 1 -v 2 ) 2450 / 2750 v 17'' v 8 +(v 7 -v 8 ) 300 / 2750 12h v 18' v 2 +(v 1 -v 2 ) 2200 / 2750 v 18'' v 8 +(v 7 -v 8 ) 550 / 2750 13h v 19' v 2 +(v 1 -v 2 ) 1950 / 2750 v 19'' v 8 +(v 7 -v 8 ) 800 / 2750 14h v 20' v 2 +(v 1 -v 2 ) 1700 / 2750 v 20'' v 8 +(v 7 -v 8 ) 1050 / 2750 15h v 21' v 2 +(v 1 -v 2 ) 1500 / 2750 v 21'' v 8 +(v 7 -v 8 ) 1250 / 2750 16h v 22' v 2 +(v 1 -v 2 ) 1300 / 2750 v 22'' v 8 +(v 7 -v 8 ) 1450 / 2750 17h v 23' v 2 +(v 1 -v 2 ) 1100 / 2750 v 23'' v 8 +(v 7 -v 8 ) 1650 / 2750 18h v 24' v 2 +(v 1 -v 2 ) 950 / 2750 v 24'' v 8 +(v 7 -v 8 ) 1800 / 2750 19h v 25' v 2 +(v 1 -v 2 ) 800 / 2750 v 25'' v 8 +(v 7 -v 8 ) 1950 / 2750 1ah v 26' v 2 +(v 1 -v 2 ) 650 / 2750 v 26'' v 8 +(v 7 -v 8 ) 2100 / 2750 1bh v 27' v 2 +(v 1 -v 2 ) 500 / 2750 v 27'' v 8 +(v 7 -v 8 ) 2250 / 2750 1ch v 28' v 2 +(v 1 -v 2 ) 400 / 2750 v 28'' v 8 +(v 7 -v 8 ) 2350 / 2750 1dh v 29' v 2 +(v 1 -v 2 ) 300 / 2750 v 29'' v 8 +(v 7 -v 8 ) 2450 / 2750 1eh v 30' v 2 +(v 1 -v 2 ) 200 / 2750 v 30'' v 8 +(v 7 -v 8 ) 2550 / 2750 1fh v 31' v 2 +(v 1 -v 2 ) 100 / 2750 v 31'' v 8 +(v 7 -v 8 ) 2650 / 2750 20h v 32' v 2 v 32'' v 7 21h v 33' v 3 +(v 2 -v 3 ) 1500 / 1600 v 33'' v 7 +(v 6 -v 7 ) 100 / 1600 22h v 34' v 3 +(v 2 -v 3 ) 1400 / 1600 v 34'' v 7 +(v 6 -v 7 ) 200 / 1600 23h v 35' v 3 +(v 2 -v 3 ) 1300 / 1600 v 35'' v 7 +(v 6 -v 7 ) 300 / 1600 24h v 36' v 3 +(v 2 -v 3 ) 1200 / 1600 v 36'' v 7 +(v 6 -v 7 ) 400 / 1600 25h v 37' v 3 +(v 2 -v 3 ) 1100 / 1600 v 37'' v 7 +(v 6 -v 7 ) 500 / 1600 26h v 38' v 3 +(v 2 -v 3 ) 1000 / 1600 v 38'' v 7 +(v 6 -v 7 ) 600 / 1600 27h v 39' v 3 +(v 2 -v 3 ) 900 / 1600 v 39'' v 7 +(v 6 -v 7 ) 700 / 1600 28h v 40' v 3 +(v 2 -v 3 ) 800 / 1600 v 40'' v 7 +(v 6 -v 7 ) 800 / 1600 29h v 41' v 3 +(v 2 -v 3 ) 700 / 1600 v 41'' v 7 +(v 6 -v 7 ) 900 / 1600 2ah v 42' v 3 +(v 2 -v 3 ) 600 / 1600 v 42'' v 7 +(v 6 -v 7 ) 1000 / 1600 2bh v 43' v 3 +(v 2 -v 3 ) 500 / 1600 v 43'' v 7 +(v 6 -v 7 ) 1100 / 1600 2ch v 44' v 3 +(v 2 -v 3 ) 400 / 1600 v 44'' v 7 +(v 6 -v 7 ) 1200 / 1600 2dh v 45' v 3 +(v 2 -v 3 ) 300 / 1600 v 45'' v 7 +(v 6 -v 7 ) 1300 / 1600 2eh v 46' v 3 +(v 2 -v 3 ) 200 / 1600 v 46'' v 7 +(v 6 -v 7 ) 1400 / 1600 2fh v 47' v 3 +(v 2 -v 3 ) 100 / 1600 v 47'' v 7 +(v 6 -v 7 ) 1500 / 1600 30h v 48' v 3 v 48'' v 6 31h v 49' v 4 +(v 3 -v 4 ) 3350 / 3450 v 49'' v 6 +(v 5 -v 6 ) 100 / 3450 32h v 50' v 4 +(v 3 -v 4 ) 3250 / 3450 v 50'' v 6 +(v 5 -v 6 ) 200 / 3450 33h v 51' v 4 +(v 3 -v 4 ) 3150 / 3450 v 51'' v 6 +(v 5 -v 6 ) 300 / 3450 34h v 52' v 4 +(v 3 -v 4 ) 3050 / 3450 v 52'' v 6 +(v 5 -v 6 ) 400 / 3450 35h v 53' v 4 +(v 3 -v 4 ) 2950 / 3450 v 53'' v 6 +(v 5 -v 6 ) 500 / 3450 36h v 54' v 4 +(v 3 -v 4 ) 2800 / 3450 v 54'' v 6 +(v 5 -v 6 ) 650 / 3450 37h v 55' v 4 +(v 3 -v 4 ) 2650 / 3450 v 55'' v 6 +(v 5 -v 6 ) 800 / 3450 38h v 56' v 4 +(v 3 -v 4 ) 2500 / 3450 v 56'' v 6 +(v 5 -v 6 ) 950 / 3450 39h v 57' v 4 +(v 3 -v 4 ) 2300 / 3450 v 57'' v 6 +(v 5 -v 6 ) 1150 / 3450 3ah v 58' v 4 +(v 3 -v 4 ) 2100 / 3450 v 58'' v 6 +(v 5 -v 6 ) 1350 / 3450 3bh v 59' v 4 +(v 3 -v 4 ) 1850 / 3450 v 59'' v 6 +(v 5 -v 6 ) 1600 / 3450 3ch v 60' v 4 +(v 3 -v 4 ) 1600 / 3450 v 60'' v 6 +(v 5 -v 6 ) 1850 / 3450 3dh v 61' v 4 +(v 3 -v 4 ) 1300 / 3450 v 61'' v 6 +(v 5 -v 6 ) 2150 / 3450 3eh v 62' v 4 +(v 3 -v 4 ) 800 / 3450 v 62'' v 6 +(v 5 -v 6 ) 2650 / 3450 3fh v 63' v 63'' out p ut volta g e1 out p ut volta g e2 v 4 v 5 caution there is no connection between v 4 and v 5 terminal in the chip. data sheet s15022ej1v0ds 9 pd16732d 6. relationship between input data and output pin data format : 6 bits x 2 rgbs (6 dots) input width : 36 bits (2-pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 ... s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 (2) r,/l = l (left shift) output s 1 s 2 s3 s4 ... s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 pol s 2n?1 note s 2n note lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 note s 2n?1 (odd output), s 2n (even output) 7. relationship between stb, pol and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. selected voltage v 0 to v 4 hi-z stb pol s 2n s 2n-1 hi-z hi-z selected voltage v 5 to v 9 selected voltage v 0 to v 4 selected voltage v 0 to v 4 selected voltage v 5 to v 9 selected voltage v 5 to v 9 data sheet s15022ej1v0ds 10 pd16732d 8. relationship between stb, clk, and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. figure 8?1. output circuit block diagram dac + output amp sw1 sn (v x ) v amp(in) - figure 8?2. output circuit block diagram stb (external input) s n (v x ) clk (external input) v amp(in) hi-z output output sw1 : on sw1 : off sw1 : on [1] [2] remarks 1. stb = l: sw1 = on stb = h: sw1 = off 2. stb = h is acknowledged at timing [1]. 3. the display data latch is completed at timing [2] and the input voltage (v amp(in) : gray-scale level voltage) of the output amplifier changes. data sheet s15022ej1v0ds 11 pd16732d 9. current consumption reduction function the pd16732d has a low power control function (lpc) which can switch the bias current of the output amplifier between two levels and a bias control function (bcont) which can be used to finely control the bias current. data sheet s15022ej1v0ds 12 pd16732d figure9 ? ? ? ? 2. output wave form (lpc = l) bcont = open output voltage(1 v/div) time (4 s / div) bcont = 1.0 k ? bcont = 10 k ? bcont = 50 k ? [1] [2] data sheet s15022ej1v0ds 13 pd16732d figure9 ? ? ? ? 3. output wave form (lpc = h) bcont = open time (4 output voltage(1 v/div) s / div) bcont = 1.0 k ? bcont = 10 k ? bcont = 50 k ? data sheet s15022ej1v0ds 14 pd16732d 10. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +4.0 v driver part supply voltage v dd2 ?0.5 to +10.0 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v driver part input voltage v i2 ?0.5 to v dd2 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v operating ambient temperature t a ?10 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic part supply voltage v dd1 2.3 3.6 v driver part supply voltage v dd2 8.0 8.5 9.0 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.3 v dd1 v v 0 to v 4 0.5 v dd2 v dd2 ? 0.1 v -corrected voltage v 5 to v 9 v ss2 + 0.1 0.5 v dd2 v driver part output voltage v o v ss2 + 0.1 v dd2 ? 0.1 v 2.3 v v dd1 < 3.0 v 45 mhz clock frequency f clk 3.0 v v dd1 3.6 v 65 mhz data sheet s15022ej1v0ds 15 pd16732d electrical characteristics (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.0 to 9.0 v, v ss1 = v ss2 = 0 v, unless otherwise specified, lpc = h or open, bcont = open) parameter symbol condition min. typ. max. unit input leak current i il 1.0 a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v -corrected resistance r v 0 to v 4 = v 5 to v 9 = 4.0 v 8 16 32 k ? i voh v x = 7.0 v, v out = 6.5 v note ?30 a driver output current i vol v x = 1.0 v, v out = 1.5 v note 30 a output voltage deviation ? v o 7 20 mv output swing difference deviation ? v p?p v dd1 = 3.3 v, v dd2 = 8.5 v v out = 2.0 v, 4.25 v, 6.5 v 2 15 mv output voltage range v o all input data 0.1 v dd2 ? 0.1 v logic part dynamic current consumption i dd1 v dd1 , with no load 1.0 6.0 ma i dd21 v dd2 = 8.0 to 9.0 v, with no load, lpc =h, bcont = open 3.0 6.0 ma driver part dynamic current consumption i dd22 v dd2 = 8.0 to 9.0 v, with no load, lpc =l, bcont = open 2.0 4.0 ma note v x refers to the output voltage of analog output pins s 1 to s 384 . v out refers to the voltage applied to analog output pins s 1 to s 384 . cautions 1. stb cycle is 20 s, f clk = 40 mhz 2. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 3. refers to the current consumption per driver when cascades are connected under the assumption of xga+ single-sided mounting (8 units). data sheet s15022ej1v0ds 16 pd16732d switching characteristics (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.0 to 9.0 v, v ss1 = v ss2 = 0 v, unless otherwise specified, lpc = h or open, bcont = open) parameter symbol condition min. typ. max. unit c l = 10 pf, 2.3 v v dd1 < 3.0 v 10 17 ns start pulse delay time t plh1 c l = 10 pf, 3.0 v v dd1 3.6 v 7 10.5 ns t plh2 2.5 5 s t plh3 58 s t phl2 2.5 5 s driver output delay time t phl3 c l = 75 pf, r l = 5 k ? 58 s c i1 exclude sthr (sthl), t a = 25c 5 10 pf input capacitance c i2 sthr (sthl),t a = 25c 8 10 pf data sheet s15022ej1v0ds 17 pd16732d switching characteristic waveform(r,/l= h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol sn (v x ) stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3646566 513 514 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage +0.1 v dd2 6-bit accuracy t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 373 to d 378 d 379 to d 384 d 385 to d 390 d 3067 to d 3072 invalid invalid v dd1 v ss1 t setup3 t hold3 pol21,pol22 (1st dr.) (1st dr.) invalid data sheet s15022ej1v0ds 18 pd16732d 11. recommended mounting conditions the following conditions must be met for mounting conditions of the pd16732d. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd16732dn- xxx : tcp (tab pack age) mounting condition mounting method condition soldering heating tool 300 to 350 c, heating for 2 to 3 seconds : pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100 c : pressure 3 to 8 kg/cm 2 : time 3 to 5 sec. real bonding 165 to 180 c: pressure 25 to 45 kg/cm 2 : time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time. data sheet s15022ej1v0ds 19 pd16732d notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. pd16732d reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of june, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? |
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